//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//++
//
// Module Name:
//
//    bvd1regs.inc
//
// Abstract:
//
//    Intel Bulverde CPU register addresses and register field definitions.
//
// Environment:
//
// Revision History:
//
//--
//
// Copyright ?2002-2003 Intel Corp.
//

.ifndef _bvd1regs_inc_
.equ _bvd1regs_inc_, 1


// ////////////////////////////////////////////////////
// /* DEVICE BASE ADDRESSES GROUPED BY FUNCTIONALITY */
// ////////////////////////////////////////////////////

//
// Internal Memory - Storage (256 KB)
//
.equ BULVERDE_BASE_REG_PA_IMSTORAGE                    ,0x5C000000

//
// Internal Memory - Control (12 B)
//
.equ BULVERDE_BASE_REG_PA_IMCONTROL                    ,0x58000000

//
// Camera Peripheral
//
.equ BULVERDE_BASE_REG_PA_CAMERA                       ,0x50000000

//
// USB Host
//
.equ BULVERDE_BASE_REG_PA_USBH                         ,0x4C000000

//
//  MEMC
//
.equ BULVERDE_BASE_REG_PA_MEMC                         ,0x48000000

//
// LCDC
//
.equ BULVERDE_BASE_REG_PA_LCD                          ,0x44000000

//
// Peripheral registers base - DMAC, UART[3:1/SIR], I2S/C, AC97, USBC, FIR,
// RTC, OST, PWM, INTC, GPIO, PWRMAN/RESETC, SSP[3:1], MMC, CLKMAN, BB, KEYPAD,
// USIM, MEMSTICK
//
.equ BULVERDE_BASE_REG_PA_PERIPH                       ,0x40000000

//
// PCMCIA Slots 0,1
//
.equ BULVERDE_BASE_REG_PA_PCMCIA_S0_IO                 ,0x20000000
.equ BULVERDE_BASE_REG_PA_PCMCIA_S0_ATTR               ,0x28000000
.equ BULVERDE_BASE_REG_PA_PCMCIA_S0_CMN                ,0x2C000000
.equ BULVERDE_BASE_REG_PA_PCMCIA_S1_IO                 ,0x30000000
.equ BULVERDE_BASE_REG_PA_PCMCIA_S1_ATTR               ,0x38000000
.equ BULVERDE_BASE_REG_PA_PCMCIA_S1_CMN                ,0x3C000000


// /////////////////////////////////////////////////////////////////////////////////////////
// /* Peripheral register offsets */
// /////////////////////////////////////////////////////////////////////////////////////////


////
////  mmr-perifs
////
.equ DMAC_OFFSET                          ,0x0             // DMA CONTROLLER
.equ FFUART_OFFSET                        ,0x00100000      // Full-Feature UART
.equ BTUART_OFFSET                        ,0x00200000      // BlueTooth UART
.equ I2C_OFFSET                           ,0x00300000      // I2C
.equ I2S_OFFSET                           ,0x00400000      // I2S
.equ AC97_OFFSET                          ,0x00500000      // AC97
.equ UDC_OFFSET                           ,0x00600000      // UDC (usb client)
.equ STUART_OFFSET                        ,0x00700000      // Standard UART
.equ FIR_OFFSET                           ,0x00800000      // FIR
.equ RTC_OFFSET                           ,0x00900000      // real time clock
.equ OST_OFFSET                           ,0x00A00000      // OS Timer
.equ PWM0_2_OFFSET                        ,0x00B00000      // PWM 0 (pulse-width mod)
.equ PWM1_3_OFFSET                        ,0x00C00000      // PWM 1 (pulse-width mod)
.equ INTC_OFFSET                          ,0x00D00000      // Interrupt controller
.equ GPIO_OFFSET                          ,0x00E00000      // GPIO
.equ PWR_OFFSET                           ,0x00F00000      // Power Manager and Reset Control
.equ SSP1_OFFSET                          ,0x01000000      // SSP 1
.equ MMC_OFFSET                           ,0x01100000      // MMC
.equ CLKMGR_OFFSET                        ,0x01300000      // Clock Manager
.equ BB_OFFSET                            ,0x01400000      // Baseband Interface
.equ KEYPAD_OFFSET                        ,0x01500000      // Keypad Interface
.equ USIM_OFFSET                          ,0x01600000      // USIM
.equ SSP2_OFFSET                          ,0x01700000      // SSP 2
.equ MEMSTK_OFFSET                        ,0x01800000      // Memory Stick
.equ SSP3_OFFSET                          ,0x01900000      // SSP 3

// /////////////////////////////////////////////////////////////////////////////////////////
// /* Relevant register-specific offsets */
// /////////////////////////////////////////////////////////////////////////////////////////

////
//// MEMC
////
.equ MDCNFG_OFFSET                        ,0x0
.equ MDREFR_OFFSET                        ,0x4
.equ MSC0_OFFSET                          ,0x8
.equ MSC1_OFFSET                          ,0xC
.equ MSC2_OFFSET                          ,0x10
.equ MECR_OFFSET                          ,0x14
.equ SXCNFG_OFFSET                        ,0x1C
.equ FLYCNFG_OFFSET                       ,0x20
.equ MCMEM0_OFFSET                        ,0x28
.equ MCMEM1_OFFSET                        ,0x2C
.equ MCATT0_OFFSET                        ,0x30
.equ MCATT1_OFFSET                        ,0x34
.equ MCIO0_OFFSET                         ,0x38
.equ MCIO1_OFFSET                         ,0x3C
.equ MDMRS_OFFSET                         ,0x40
.equ BOOT_DEF_OFFSET                      ,0x44
.equ ARB_CNTL_OFFSET                      ,0x48
.equ BSCNTR0_OFFSET                       ,0x4C
.equ BSCNTR1_OFFSET                       ,0x50
.equ LCDBSCNTR_OFFSET                     ,0x54
.equ MDMRSLP_OFFSET                       ,0x58
.equ BSCNTR2_OFFSET                       ,0x5C
.equ BSCNTR3_OFFSET                       ,0x60

////
//// FULL-FEATURE UART
////
.equ FF_THR_OFFSET                        ,0x0       //DLAB = 0  WO  8bit - Transmit Holding Register
.equ FF_RBR_OFFSET                        ,0x0       //DLAB = 0  RO  8bit - Receive Buffer Register
.equ FF_DLL_OFFSET                        ,0x0       //DLAB = 1  RW  8bit - Divisor Latch Low Register
.equ FF_IER_OFFSET                        ,0x4       //DLAB = 0  RW  8bit - Interrupt Enable Register
.equ FF_DLH_OFFSET                        ,0x4       //DLAB = 1  RW  8bit - Divisor Latch High Register
.equ FF_IIR_OFFSET                        ,0x8       //DLAB = X  RO  8bit - Interrupt Identification Register
.equ FF_FCR_OFFSET                        ,0x8       //DLAB = X  WO  8bit - FIFO Control Register
.equ FF_LCR_OFFSET                        ,0xC       //DLAB = X  RW  8bit - Line Control Register
.equ FF_MCR_OFFSET                        ,0x10      //DLAB = X  RW  8bit - Modem Control Regiser
.equ FF_LSR_OFFSET                        ,0x14      //DLAB = X  RO  8bit - Line Status Register
.equ FF_MSR_OFFSET                        ,0x18      //DLAB = X  RO  8bit - Modem Status Register
.equ FF_SPR_OFFSET                        ,0x1C      //DLAB = X  RW  8bit - Scratchpad Register
.equ FF_ISR_OFFSET                        ,0x20      //DLAB = X  RW  8bit - Slow Infrared Select Register
.equ FF_FOR_OFFSET                        ,0x24      //DLAB = X  RO  FIFO Occupancy Register
.equ FF_ABR_OFFSET                        ,0x28      //DLAB = X  RW  Autobaud Control Register
.equ FF_ACR_OFFSET                        ,0x2C      //DLAB = X Autobaud Count Register

////
//// BLUETOOTH UART
////
.equ BT_THR_OFFSET                        ,0x0       //DLAB = 0  WO  8bit - Transmit Holding Register
.equ BT_RBR_OFFSET                        ,0x0       //DLAB = 0  RO  8bit - Receive Buffer Register
.equ BT_DLL_OFFSET                        ,0x0       //DLAB = 1  RW  8bit - Divisor Latch Low Register
.equ BT_IER_OFFSET                        ,0x4       //DLAB = 0  RW  8bit - Interrupt Enable Register
.equ BT_DLH_OFFSET                        ,0x4       //DLAB = 1  RW  8bit - Divisor Latch High Register
.equ BT_IIR_OFFSET                        ,0x8       //DLAB = X  RO  8bit - Interrupt Identification Register
.equ BT_FCR_OFFSET                        ,0x8       //DLAB = X  WO  8bit - FIFO Control Register
.equ BT_LCR_OFFSET                        ,0xC       //DLAB = X  RW  8bit - Line Control Register
.equ BT_MCR_OFFSET                        ,0x10      //DLAB = X  RW  8bit - Modem Control Regiser
.equ BT_LSR_OFFSET                        ,0x14      //DLAB = X  RO  8bit - Line Status Register
.equ BT_MSR_OFFSET                        ,0x18      //DLAB = X  RO  8bit - Modem Status Register
.equ BT_SPR_OFFSET                        ,0x1C      //DLAB = X  RW  8bit - Scratchpad Register
.equ BT_ISR_OFFSET                        ,0x20      //DLAB = X  RW  8bit - Slow Infrared Select Register
.equ BT_FOR_OFFSET                        ,0x24      //DLAB = X  RO  FIFO Occupancy Register
.equ BT_ABR_OFFSET                        ,0x28      //DLAB = X  RW  Autobaud Control Register
.equ BT_ACR_OFFSET                        ,0x2C      //DLAB = X Autobaud Count Register

////
//// STANDARD UART
////
.equ ST_THR_OFFSET                        ,0x0       //DLAB = 0  WO  8bit - Transmit Holding Register
.equ ST_RBR_OFFSET                        ,0x0       //DLAB = 0  RO  8bit - Receive Buffer Register
.equ ST_DLL_OFFSET                        ,0x0       //DLAB = 1  RW  8bit - Divisor Latch Low Register
.equ ST_IER_OFFSET                        ,0x4       //DLAB = 0  RW  8bit - Interrupt Enable Register
.equ ST_DLH_OFFSET                        ,0x4       //DLAB = 1  RW  8bit - Divisor Latch High Register
.equ ST_IIR_OFFSET                        ,0x8       //DLAB = X  RO  8bit - Interrupt Identification Register
.equ ST_FCR_OFFSET                        ,0x8       //DLAB = X  WO  8bit - FIFO Control Register
.equ ST_LCR_OFFSET                        ,0xC       //DLAB = X  RW  8bit - Line Control Register
.equ ST_MCR_OFFSET                        ,0x10      //DLAB = X  RW  8bit - Modem Control Regiser
.equ ST_LSR_OFFSET                        ,0x14      //DLAB = X  RO  8bit - Line Status Register
.equ ST_MSR_OFFSET                        ,0x18      //DLAB = X  RO  8bit - Modem Status Register
.equ ST_SPR_OFFSET                        ,0x1C      //DLAB = X  RW  8bit - Scratchpad Register
.equ ST_ISR_OFFSET                        ,0x20      //DLAB = X  RW  8bit - Slow Infrared Select Register
.equ ST_FOR_OFFSET                        ,0x24      //DLAB = X  RO  FIFO Occupancy Register
.equ ST_ABR_OFFSET                        ,0x28      //DLAB = X  RW  Autobaud Control Register
.equ ST_ACR_OFFSET                        ,0x2C      //DLAB = X Autobaud Count Register

////
//// RTC
////
.equ RCNR_OFFSET                          ,0x0       //RTC count register
.equ RTAR_OFFSET                          ,0x4       //RTC alarm register
.equ RTSR_OFFSET                          ,0x8       //RTC status register
.equ RTTR_OFFSET                          ,0xC       //RTC timer trim register
.equ RDCR_OFFSET                          ,0x10      //RTC Day Counter
.equ RYCR_OFFSET                          ,0x14      //RTC Year Counter
.equ RDAR1_OFFSET                         ,0x18      //RTC Day Alarm 1
.equ RYAR1_OFFSET                         ,0x1C      //RTC Year Alarm 1
.equ RDAR2_OFFSET                         ,0x20      //RTC Day Alarm 2
.equ RYAR2_OFFSET                         ,0x24      //RTC Year Alarm 2
.equ SWCR_OFFSET                          ,0x28      //RTC Stopwatch Counter
.equ SWAR1_OFFSET                         ,0x2C      //RTC Stopwatch Alarm 1
.equ SWAR2_OFFSET                         ,0x30      //RTC Stopwatch Alarm 2
.equ PICR_OFFSET                          ,0x34      //RTC Periodic Interrupt Counter
.equ PIAR_OFFSET                          ,0x38      //RTC Periodic Interrupt Alarm


////
//// OST (OS TIMER)
////
.equ OSMR0_OFFSET                         ,0x0       //OS timer match register 0
.equ OSMR1_OFFSET                         ,0x4       //OS timer match register 1
.equ OSMR2_OFFSET                         ,0x8       //OS timer match register 2
.equ OSMR3_OFFSET                         ,0xC       //OS timer match register 3
.equ OSCR0_OFFSET                         ,0x10      //OS timer counter register 0
.equ OSSR_OFFSET                          ,0x14      //OS timer status register
.equ OWER_OFFSET                          ,0x18      //OS timer watchdog enable register
.equ OIER_OFFSET                          ,0x1C      //OS timer interrupt enable register
.equ OSCR4_OFFSET                         ,0x40
.equ OSCR5_OFFSET                         ,0x44
.equ OSCR6_OFFSET                         ,0x48
.equ OSCR7_OFFSET                         ,0x4C
.equ OSCR8_OFFSET                         ,0x50
.equ OSCR9_OFFSET                         ,0x54
.equ OSCR10_OFFSET                        ,0x58
.equ OSCR11_OFFSET                        ,0x5C
.equ OSMR4_OFFSET                         ,0x80
.equ OSMR5_OFFSET                         ,0x84
.equ OSMR6_OFFSET                         ,0x88
.equ OSMR7_OFFSET                         ,0x8C
.equ OSMR8_OFFSET                         ,0x90
.equ OSMR9_OFFSET                         ,0x94
.equ OSMR10_OFFSET                        ,0x98
.equ OSMR11_OFFSET                        ,0x9C
.equ OMCR4_OFFSET                         ,0xC0
.equ OMCR5_OFFSET                         ,0xC4
.equ OMCR6_OFFSET                         ,0xC8
.equ OMCR7_OFFSET                         ,0xCC
.equ OMCR8_OFFSET                         ,0xD0
.equ OMCR9_OFFSET                         ,0xD4
.equ OMCR10_OFFSET                        ,0xD8
.equ OMCR11_OFFSET                        ,0xDC


////
//// INTC (INTERRUPT CONTROLLER) - Memory-mapped addresses (can also use c-proc for most of these)
////
.equ ICIP_OFFSET                          ,0x0       //Interrupt controller IRQ pending register
.equ ICMR_OFFSET                          ,0x4       //Interrupt controller mask register
.equ ICLR_OFFSET                          ,0x8       //Interrupt controller level register
.equ ICFP_OFFSET                          ,0xC       //Interrupt controller FIQ pending register
.equ ICPR_OFFSET                          ,0x10      //Interrupt controller pending register
.equ ICCR_OFFSET                          ,0x14      //Interrupt controller control register
.equ ICHP_OFFSET                          ,0x18      //Interrupt controller Highest Priority register
.equ IPR0_OFFSET                          ,0x1C      //Interrupt controller Priority registerS [31:0]
.equ IPR1_OFFSET                          ,0x20
.equ IPR2_OFFSET                          ,0x24
.equ IPR3_OFFSET                          ,0x28
.equ IPR4_OFFSET                          ,0x2C
.equ IPR5_OFFSET                          ,0x30
.equ IPR6_OFFSET                          ,0x34
.equ IPR7_OFFSET                          ,0x38
.equ IPR8_OFFSET                          ,0x3C
.equ IPR9_OFFSET                          ,0x40
.equ IPR10_OFFSET                         ,0x44
.equ IPR11_OFFSET                         ,0x48
.equ IPR12_OFFSET                         ,0x4C
.equ IPR13_OFFSET                         ,0x50
.equ IPR14_OFFSET                         ,0x54
.equ IPR15_OFFSET                         ,0x58
.equ IPR16_OFFSET                         ,0x5C
.equ IPR17_OFFSET                         ,0x60
.equ IPR18_OFFSET                         ,0x64
.equ IPR19_OFFSET                         ,0x68
.equ IPR20_OFFSET                         ,0x6C
.equ IPR21_OFFSET                         ,0x70
.equ IPR22_OFFSET                         ,0x74
.equ IPR23_OFFSET                         ,0x78
.equ IPR24_OFFSET                         ,0x7C
.equ IPR25_OFFSET                         ,0x80
.equ IPR26_OFFSET                         ,0x84
.equ IPR27_OFFSET                         ,0x88
.equ IPR28_OFFSET                         ,0x8C
.equ IPR29_OFFSET                         ,0x90
.equ IPR30_OFFSET                         ,0x94
.equ IPR31_OFFSET                         ,0x98

////
//// GPIO
////
.equ GPLR0_OFFSET                         ,0x0       //GPIO pin-level register 31:0
.equ GPLR1_OFFSET                         ,0x4       //GPIO pin-level register 63:32
.equ GPLR2_OFFSET                         ,0x8       //GPIO pin-level register 95:64
.equ GPDR0_OFFSET                         ,0xC       //GPIO pin-direction register 31:0
.equ GPDR1_OFFSET                         ,0x10      //GPIO pin-direction register 63:32
.equ GPDR2_OFFSET                         ,0x14      //GPIO pin-direction register 95:64
.equ GPSR0_OFFSET                         ,0x18      //GPIO pin output set register 31:0
.equ GPSR1_OFFSET                         ,0x1C      //GPIO pin output set register 63:32
.equ GPSR2_OFFSET                         ,0x20      //GPIO pin output set register 95:64
.equ GPCR0_OFFSET                         ,0x24      //GPIO pin output clear register 31:0
.equ GPCR1_OFFSET                         ,0x28      //GPIO pin output clear register 63:32
.equ GPCR2_OFFSET                         ,0x2C      //GPIO pin output clear register 95:64
.equ GRER0_OFFSET                         ,0x30      //GPIO rising edge detect register 31:0
.equ GRER1_OFFSET                         ,0x34      //GPIO rising edge detect register 63:32
.equ GRER2_OFFSET                         ,0x38      //GPIO rising edge detect register 95:64
.equ GFER0_OFFSET                         ,0x3C      //GPIO falling edge detect register 31:0
.equ GFER1_OFFSET                         ,0x40      //GPIO falling edge detect register 63:32
.equ GFER2_OFFSET                         ,0x44      //GPIO falling edge detect register 95:64
.equ GEDR0_OFFSET                         ,0x48      //GPIO edge detect status register 31:0
.equ GEDR1_OFFSET                         ,0x4C      //GPIO edge detect status register 63:32
.equ GEDR2_OFFSET                         ,0x50      //GPIO edge detect status register 95:64
.equ GAFR0_L_OFFSET                       ,0x54      //GPIO alternate funciton select register 15:0
.equ GAFR0_U_OFFSET                       ,0x58      //GPIO alternate function select register 31:16
.equ GAFR1_L_OFFSET                       ,0x5C      //GPIO alternate function select register 47:32
.equ GAFR1_U_OFFSET                       ,0x60      //GPIO alternate function select register 63:48
.equ GAFR2_L_OFFSET                       ,0x64      //GPIO alternate function select register 79:64
.equ GAFR2_U_OFFSET                       ,0x68      //GPIO alternate function select register 95:80
.equ GAFR3_L_OFFSET                       ,0x6C      //GPIO alternate function select register 111:96
.equ GAFR3_U_OFFSET                       ,0x70      //GPIO alternate function select register 120:112
.equ GPLR3_OFFSET                         ,0x100     //GPIO pin-level register 120:96
.equ GPDR3_OFFSET                         ,0x10C     //GPIO pin-direction register 120:96
.equ GPSR3_OFFSET                         ,0x118     //GPIO pin output set register 120:96
.equ GPCR3_OFFSET                         ,0x124     //GPIO pin output clear register 120:96
.equ GRER3_OFFSET                         ,0x130     //GPIO rising edge detect register 120:96
.equ GFER3_OFFSET                         ,0x13C     //GPIO falling edge detect register 120:96
.equ GEDR3_OFFSET                         ,0x148     //GPIO edge detect status register 120:96


////
//// POWER MANAGER & RESET CONTROLLER
////
.equ PMCR_OFFSET                          ,0x0       //Power manager control register
.equ PSSR_OFFSET                          ,0x4       //Power manager sleep status register
.equ PSPR_OFFSET                          ,0x8       //Power manager scratch pad register
.equ PWER_OFFSET                          ,0xC       //Power manager wake-up enable register
.equ PRER_OFFSET                          ,0x10      //Power manager GPIO rising edge detect enable register
.equ PFER_OFFSET                          ,0x14      //Power manager GPIO falling edge detect enable register
.equ PEDR_OFFSET                          ,0x18      //Power manager GPIO edge detect status register
.equ PCFR_OFFSET                          ,0x1C      //Power manager general configuration register
.equ PGSR0_OFFSET                         ,0x20      //Power manager GPIO sleep state register for GPIO 31:0
.equ PGSR1_OFFSET                         ,0x24      //Power manager GPIO sleep state register for GPIO 63:32
.equ PGSR2_OFFSET                         ,0x28      //Power manager GPIO sleep state register for GPIO 95:64
.equ PGSR3_OFFSET                         ,0x2C      //Power manager GPIO sleep state register for GPIO 120:96
.equ RCSR_OFFSET                          ,0x30      // **Reset controller status register**
.equ PSLR_OFFSET                          ,0x34      //Power manager Sleep Mode Config
.equ PSTR_OFFSET                          ,0x38      //Power manager Standby Mode Config
.equ PSNR_OFFSET                          ,0x3C      //Power manager Sense Mode Config
.equ PVCR_OFFSET                          ,0x40      //Power manager Voltage Change Control
.equ PCMD0_OFFSET                         ,0x80      //Power manager I2C Command[31:0]
.equ PCMD1_OFFSET                         ,0x84
.equ PCMD2_OFFSET                         ,0x88
.equ PCMD3_OFFSET                         ,0x8C
.equ PCMD4_OFFSET                         ,0x90
.equ PCMD5_OFFSET                         ,0x94
.equ PCMD6_OFFSET                         ,0x98
.equ PCMD7_OFFSET                         ,0x9C
.equ PCMD8_OFFSET                         ,0xA0
.equ PCMD9_OFFSET                         ,0xA4
.equ PCMD10_OFFSET                        ,0xA8
.equ PCMD11_OFFSET                        ,0xAC
.equ PCMD12_OFFSET                        ,0xB0
.equ PCMD13_OFFSET                        ,0xB4
.equ PCMD14_OFFSET                        ,0xB8
.equ PCMD15_OFFSET                        ,0xBC
.equ PCMD16_OFFSET                        ,0xC0
.equ PCMD17_OFFSET                        ,0xC4
.equ PCMD18_OFFSET                        ,0xC8
.equ PCMD19_OFFSET                        ,0xCC
.equ PCMD20_OFFSET                        ,0xD0
.equ PCMD21_OFFSET                        ,0xD4
.equ PCMD22_OFFSET                        ,0xD8
.equ PCMD23_OFFSET                        ,0xDC
.equ PCMD24_OFFSET                        ,0xE0
.equ PCMD25_OFFSET                        ,0xE4
.equ PCMD26_OFFSET                        ,0xE8
.equ PCMD27_OFFSET                        ,0xEC
.equ PCMD28_OFFSET                        ,0xF0
.equ PCMD29_OFFSET                        ,0xF4
.equ PCMD30_OFFSET                        ,0xF8
.equ PCMD31_OFFSET                        ,0xFC
.equ PIBMR_OFFSET                         ,0x180     //Power manager I2C Bus Monitor
.equ PIDBR_OFFSET                         ,0x188     //Power manager I2C Data Buffer
.equ PI2CR_OFFSET                         ,0x190     //Power manager I2C Control
.equ PISR_OFFSET                          ,0x198     //Power manager I2C Status
.equ PISAR_OFFSET                         ,0x1A0     //Power manager I2C Slave Address


////
//// CLK MANAGER
////
.equ CCCR_OFFSET                          ,0x0       //Core Clock Configuration Register
.equ CKEN_OFFSET                          ,0x4       //Clock Enable Register
.equ OSCC_OFFSET                          ,0x8       //Oscillator Configuration Register
.equ CCSR_OFFSET                          ,0xC       //Core Clock Status


// /////////////////////////////////////////////////////////////////////////////////////////
// /* Peripheral-specific base addresses */
// /////////////////////////////////////////////////////////////////////////////////////////

.equ BULVERDE_BASE_REG_PA_FFUART          ,(BULVERDE_BASE_REG_PA_PERIPH + FFUART_OFFSET)
.equ BULVERDE_BASE_REG_PA_BTUART          ,(BULVERDE_BASE_REG_PA_PERIPH + BTUART_OFFSET)
.equ BULVERDE_BASE_REG_PA_STUART          ,(BULVERDE_BASE_REG_PA_PERIPH + STUART_OFFSET)
.equ BULVERDE_BASE_REG_PA_RTC             ,(BULVERDE_BASE_REG_PA_PERIPH + RTC_OFFSET)
.equ BULVERDE_BASE_REG_PA_OST             ,(BULVERDE_BASE_REG_PA_PERIPH + OST_OFFSET)
.equ BULVERDE_BASE_REG_PA_INTC            ,(BULVERDE_BASE_REG_PA_PERIPH + INTC_OFFSET)
.equ BULVERDE_BASE_REG_PA_GPIO            ,(BULVERDE_BASE_REG_PA_PERIPH + GPIO_OFFSET)
.equ BULVERDE_BASE_REG_PA_PWR             ,(BULVERDE_BASE_REG_PA_PERIPH + PWR_OFFSET)
.equ BULVERDE_BASE_REG_PA_CLKMGR          ,(BULVERDE_BASE_REG_PA_PERIPH + CLKMGR_OFFSET)


.equ RCSR_ALL                             ,0x1F
.equ Mode_SVC                             ,0x13
.equ Mode_USR                             ,0x10
.equ NoIntsMask                           ,0x000000C0
.equ IRQIntsMask                          ,0x7F      // 0=enabled, 1=disabled
.equ IrqFiqEnable                         ,0xFFFFFF3F

//
// FLASH constants
//
.equ K3_128Mb_DEVCODE                     ,0x8806
.equ J3_128Mb_DEVCODE                     ,0x18
.equ L3_128Mb_DEVCODE                     ,0x880C

//
// Reset Controller Status Register bit defines
//
.equ RCSR_HARD_RESET                      ,(0x1)
.equ RCSR_WDOG_RESET                      ,(0x1 << 1)
.equ RCSR_SLEEP_RESET                     ,(0x1 << 2)
.equ RCSR_GPIO_RESET                      ,(0x1 << 3)
.equ PSSR_VALID_MASK                      ,(0x3F)
.equ PSSR_RDH                             ,(0x1 << 5)
.equ PSSR_PH                              ,(0x1 << 4)

//
// Clock Manager Defs
//
.equ OSCC_OOK                             ,(0x1)
.equ OSCC_OON                             ,(0x1 << 1)
.equ OSCC_TOUT_EN                         ,(0x1 << 2)
.equ OSCC_PIO_EN                          ,(0x1 << 3)
.equ OSCC_CRI                             ,(0x1 << 4)
.equ CKEN_DEFAULT                         ,0x00400200        // MEMC, OST clocked.  Rest OFF

//
//  Power Manager Defs
//
.equ PCFR_OPDE                            ,(0x1)
.equ PCFR_FP                              ,(0x1 << 1)
.equ PCFR_FS                              ,(0x1 << 2)
.equ PCFR_GPR_EN                          ,(0x1 << 4)
.equ PCFR_SYSEN_EN                        ,(0x1 << 5)
.equ PCFR_PI2C_EN                         ,(0x1 << 6)
.equ PCFR_DC_EN                           ,(0x1 << 7)
.equ PCFR_FVC                             ,(0x1 << 10)
.equ PCFR_L1_EN                           ,(0x1 << 11)
.equ PCFR_GP_ROD                          ,(0x1 << 12)
.equ PWER_WE0                             ,(0x1)
.equ PWER_WE1                             ,(0x1 << 1)
.equ PWER_WBB                             ,(0x1 << 25)
.equ PWER_WEUSBC                          ,(0x1 << 26)
.equ PWER_WEUSBH0                         ,(0x1 << 27)
.equ PWER_WEUSBH1                         ,(0x1 << 28)
.equ PWER_WEP1                            ,(0x1 << 30)
.equ PWER_WERTC                           ,(0x1 << 31)
.equ PMCR_BIDAE                           ,(0x1)
.equ PMCR_BIDAS                           ,(0x1 << 1)
.equ PMCR_VIDAE                           ,(0x1 << 2)
.equ PMCR_VIDAS                           ,(0x1 << 3)
.equ PMCR_IAS                             ,(0x1 << 4)
.equ PMCR_INTRS                           ,(0x1 << 5)

//
//  Bits used for Memory Controller Init
//
// register bit masks - mdcnfg
.equ MDCNFG_DE0                           ,(0x1 << 0)
.equ MDCNFG_DE1                           ,(0x1 << 1)
.equ MDCNFG_DWID0                         ,(0x1 << 2)
.equ MDCNFG_DCAC0                         ,(0x3 << 3)
.equ MDCNFG_DRAC0                         ,(0x3 << 5)
.equ MDCNFG_DNB0                          ,(0x1 << 7)
.equ MDCNFG_DTC0                          ,(0x3 << 8)
.equ MDCNFG_DADDR0                        ,(0x1 << 10)
.equ MDCNFG_DLATCH0                       ,(0x1 << 11)
.equ MDCNFG_RESERVED0                     ,(0xF << 12)
.equ MDCNFG_DE2                           ,(0x1 << 16)
.equ MDCNFG_DE3                           ,(0x1 << 17)
.equ MDCNFG_DWID2                         ,(0x1 << 18)
.equ MDCNFG_DCAC2                         ,(0x3 << 19)
.equ MDCNFG_DRAC2                         ,(0x3 << 21)
.equ MDCNFG_DNB2                          ,(0x1 << 23)
.equ MDCNFG_DTC2                          ,(0x3 << 24)
.equ MDCNFG_DADDR2                        ,(0x1 << 26)
.equ MDCNFG_DLATCH2                       ,(0x1 << 27)
.equ MDCNFG_RESERVED2                     ,(0xF << 28)

.equ MDREFR_E0PIN                         ,0x00001000
.equ MDREFR_K0RUN                         ,0x00002000
.equ MDREFR_K1RUN                         ,0x00010000
.equ MDREFR_K2RUN                         ,0x00040000
.equ MDREFR_SLFRSH                        ,0x00400000
.equ MDREFR_E1PIN                         ,0x00008000
.equ MDREFR_K1DB2                         ,0x00020000    // run SDCLK[1] @ .5(MClk)
.equ MDREFR_K0DB2                         ,0x00004000
.equ MDREFR_K0DB4                         ,0x20000000    // run SDCLK[0] @ .25(MemClk)
.equ MDREFR_K0FREE                        ,0x00800000
.equ MDREFR_K1FREE                        ,0x01000000
.equ MDREFR_K2FREE                        ,0x02000000
.equ MDREFR_APD                           ,0x00100000
.equ BANK_SHIFT                           ,20

//
//   Bits used for the HWConfig Reg (aka PowerManager.ScratchPad)
//
.equ HWConfig_RESET                       ,(0x1  <<  0)
.equ HWCONFIG_DEFAULT                     ,(0x01155046)
.equ HWConfig_BootromPM                   ,(0x1  <<  12)
.equ PAGEMODE_ON                          ,(0x1)

//
//   Bits used for CP 15
//
.equ CONTROL_MMU                          ,0x00000001

.endif // .ifndef _bvd1regs_inc_

